spt7830 10-bit , 2.5 msps, serial output a/d converter 10-bit a/d analog input v ref+ serial output logic ground v dd sar clock data out start convert aaaaaaaaaaaaaaaaa a aaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaa a aaaaaaaaaaaaaaaaa track-and-hold v ref- timing and control block diagram features ? 10-bit, 1 khz to 2.5 msps analog-to-digital converter ? monolithic cmos ? serial output ? internal sample-and-hold ? analog input range: 0 to 2 v nominal; 3.3 v max ? power dissipation (excluding reference ladder) 45 mw at +5 v 16 mw at +3.0 v ? single power supply: +3 v to +5 v range ? high esd protection: 3,000 v minimum applications ? handheld and desktop scanners ? dsp interface applications ? portable digital radios ? portable and handheld applications ? automotive applications ? remote sensing general description the spt7830 10-bit, 2.5 msps, serial analog-to-digital converter delivers excellent high speed conversion perfor- mance with low cost and low power. the serial port protocol is compatible with the serial peripheral interface (spi) or microwire? industry standard, high-speed synchronous mpu interfaces. the large input bandwidth and fast transient response time allow for ccd applications operating up to 2.5 msps. the device can operate with a power supply range from + 3 v to +5 v with very low power dissipation. the small package size makes this part excellent for hand-held appli- cations where board space is at a premium. the spt7830 is available in an 8-lead soic package over the commercial and industrial temperature ranges. contact the factory for availability of die.
2 12/29/99 spt7830 electrical specifications t a = +25 c, v dd = +5.0 v, v in = 0 to +3 v, f clk = 35 mhz, f s = 2.5 msps, v ref + = +3.0 v, v ref C = 0.0 v, unless otherwise specified. test test parameters conditions level min typ max units dc electrical characteristics dc performance resolution 10 bits differential linearity vi 0.5 1.0 lsb integral linearity vi 1.0 1.5 lsb no missing codes vi guaranteed analog input input voltage range 1 iv v ref C +4% v ref + C6% v input resistance vi 5 m w input capacitance iv 5 pf input bandwidth (small signal) iv 30 mhz offset iv C2 +2 % of fsr gain error iv C2 +2 % of fsr reference input resistance iv 250 280 350 w voltage range 1 v ref C 2 iv C4% 0 v ref + C d v v ref + 2 iv v ref C + d 2/3 v dd v v ref + C v ref C ( d ) iv 1/10 v dd v reference settling time iv 90 ns timing characteristics maximum conversion rate vi 2.5 1.0 msps minimum conversion rate iv 1 ksps maximum external clock rate vi 35 14 mhz minimum external clock rate iv 14 khz aperture delay time iv 5 ns aperture jitter time iv 5 ps data output lsb hold time t min to t max iv 6 8 ns supply voltages v dd ...........................................................................+6 v input voltages analog input ................................................ C0.7 to +6 v v ref + .......................................................... C0.7 to +6 v v ref C .......................................................... C0.7 to +6 v clock and sc .............................................. C0.7 to +6 v output data out ................................................................ 10 ma temperature operating, ambient ............................... C40 to +85 c junction ......................................... +175 c lead, soldering (10 seconds) ............................ +300 c storage .................................................... C65 to +150 c note : 1. operation at any absolute maximum ratings is not implied. see electrical specifications for proper nominal applied conditions in typical applications. 1 percentages refer to percent of [(v ref +) C (v ref C)] 2 d = minimum (v ref + C v ref C) absolute maximum rating (beyond which damage may occur) 1
3 12/29/99 spt7830 electrical specifications t a = +25 c, v dd = +5.0 v, v in = 0 to +3 v, f clk = 35 mhz, f s = 2.5 msps, v ref + = +3.0 v, v ref C = 0.0 v, unless otherwise specified. test test parameters conditions level min typ max units dynamic performance effective number of bits f in = 500 khz iv 8.9 bits f in = 1 mhz iv 8.5 bits signal-to-noise ratio f in = 500 khz iv 56 db f in = 1 mhz iv 55 db harmonic distortion f in = 500 khz iv 63 db f in = 1 mhz iv 58 db power supply requirements +v dd supply voltage iv 3 5.5 v +v dd supply current v dd = +3.0 v iv 5.4 7 ma v dd = +5.0 v vi 9 10 ma power dissipation 3 v dd = +3.0 v iv 16 22 mw v dd = +5.0 v vi 45 50 mw 3 excluding reference ladder. test level codes all electrical characteristics are subject to the following conditions: all parameters having min/max specifications are guaranteed. the test level column indi- cates the specific device testing actually per- formed during production and quality assur- ance inspection. any blank section in the data column indicates that the specification is not tested at the specified condition. test procedure 100% production tested at the specified temperature. 100% production tested at t a =+25 c, and sample tested at the specified temperatures. qa sample tested only at the specified temperatures. parameter is guaranteed (but not tested) by design and characterization data. parameter is a typical value for information purposes only. 100% production tested at t a = +25 c. parameter is guaranteed over specified temperature range. test level i ii iii iv v vi
4 12/29/99 spt7830 should be taken to ensure that the lsb is latched into an external latch with the proper amount of set and hold time. data output coding the coding of the output is straight binary. (see table i.) table i - data output coding analog input output code d9 - do +fs -1/2 lsb 1 1 1111 111? +1/2 fs ? x xxxx xxxx +1/2 lsb oo oooo ooo? v ref- oo oooo oooo ? indicates the flickering bit between logic o and 1. x indicates the flickering bit between logic 1 and o. analog input and reference settling track and hold timing figure 9 shows the timing relationship between the input clock and sc versus the analog input tracking and reference settling. the analog input is tracked from the fourteenth clock cycle of the previous conversion to the third clock cycle of the current conversion. on the falling edge of the third clock cycle, the analog input is held by the internal sample-and- hold. after this sample, the analog input may vary without affecting data conversion. the reference ladder inputs (v ref + and v ref -) may be changed starting on the falling edge of the thirteenth clock cycle of the previous conversion and must be settled by the falling edge of the third clock cycle of the current conversion. voltage reference and analog input the spt7830 requires the use of a single external voltage reference for driving the high side of the reference ladder. the v ref + can be a maximum of 2/3 v dd . for example, if v dd = +5 v, then v ref + max = (2/3) * 5 v = +3.3 v. the lower side of the ladder is typically tied to agnd (0.0 v), but can be run up to a voltage that is 1/10th of v dd below v ref +: v ref - max. = v ref + - (1/10) * v dd . for example, if v dd = +5 v and v ref + = 3 v, then v ref - max = 3 v - (1/10) * 5 v = 2.5 v. the +full scale (+fs) of the analog input is expected to be 6 % of [(v ref +) - (v ref -)] below v ref + and the -full scale (-fs) of the analog input is expected to be 4% of [(v ref +) - (v ref -)] above v ref -. (see figure 1.) therefore, analog +fs = v ref + - 0.06 * [(v ref +) - (v ref -)], and analog -fs = v ref - +0.04 * [(v ref +) - (v ref -)]. for example, if v ref + = 3 v and v ref - = 0 v, then analog +fs = 3 v - 0.06 * [3 v- 0 v ] = 2.82 v, and analog -fs = 0 v + 0.04 * [3 v - 0 v] = 0.12 v. general description and operation the spt7830 is a 10-bit analog-to-digital converter that uses a successive approximation architecture to perform data conversion. each conversion cycle is 14 clocks in length. when the not start convert ( sc ) line is held low, conversion begins on the next rising edge of the input clock. when the conversion cycle begins, the data output pin is forced low until valid data output begins. the first two clock cycles are used to perform internal offset calibrations and tracking of the analog input. the analog input is then sampled using an internal track-and-hold amplifier on the falling edge of the third clock cycle. on clock cycles 4 through 14, a 10-bit successive approximation conversion is performed, and the data is output starting with the msb. serial data output begins with output of the msb. see the data output timing section for details. each bit of the data conversion is sequentially determined and placed on the data output pin at the clock rate. this process continues until the lsb has been determined and output. at this point, if the sc line is high, the data output pin will be forced into a high impedance state, and the converter will go into an idle state waiting for the sc line to go low. this is referred to as single shot mode. see modes of operation for details. if the sc is either held low through the entire 14 clock conversion cycle (free run mode) or is brought low prior to the trailing edge of the fourteenth clock cycle (synchronous mode), the data output pin goes low and stays low until valid data output begins. because the chip has either remained selected in the free run mode or has been immediately selected again in the synchronous mode, the next conversion cycle begins immediately after the fourteenth clock cycle of the previous conversion. see modes of operation for details. typical interface circuit clock input the spt7830 requires a 50% 10% duty cycle clock running at 14 times the desired sample rate. the clock may be stopped in between conversion cycles without degradation of operation (single shot type of operation); however, the clock should remain running during a conversion cycle. power supply the spt7830 requires only a single supply and operates capacitor be placed as close as possible to the supply pin. data output set up and hold timing as figure 8 shows, all of the data output bits (except the lsb) remain valid for a duration equivalent to one clock period and delayed by 8 ns after the falling edge of clock. because the data converter enters into a next conversion ready state at the leading edge of clock 14, the lsb bit is valid for a duration equivalent to only the clock pulse width low and delayed by 8 ns after the falling edge of clock. care from 3.0 v to 5.0 v. cadeka recommends that a 0.01 m f chip
5 12/29/99 spt7830 figure 1 - analog input full-scale range v ref + 6% of [(v ref +) - (v ref -)] v ref - +fs -fs full-scale range 4% of [(v ref +) - (v ref -)] the drive requirements for the analog input are minimal when compared to most other converters due to the spt7830s extremely low input capacitance of only 5 pf and very high input resistance of greater than 5 m w . if the input buffer amplifier supply voltages are greater than v dd + 0.7 v or less than ground - 0.7 v, the analog input should be protected through a series resistor and a diode clamping circuit as shown in figure 2. figure 2 - recommended input protection circuit 47 w d1 d2 adc buffer av dd +v -v d1 = d2 = hewlett packard hp5712 or equivalent input protection all i/o pads are protected with an on-chip protection circuit shown in figure 3. this circuit provides esd robustness to >3.0 kv and prevents latch-up under severe discharge conditions without degrading analog transition times. figure 3 - on-chip protection circuit v dd analog pad 120 w 120 w modes of operation the spt7830 has three modes of operation.the mode of operation is based strictly on how the sc is used. single shot mode when sc goes low, conversion starts on the next rising edge of the clock (defined as the first conversion clock). the msb of data is valid 8 ns after the falling edge of the fourth conversion clock. (see figure 8, data output timing.) the conversion is complete after 14 clock cycles. at the falling edge of the fourteenth clock cycle, if sc is high (not selected), the data output goes to a high impedance state, and no more conversions will take place until the next sc low event. (see the single shot mode timing diagram in figure 4.) synchronized mode when sc goes low, conversion will start on the next rising edge of the clock (defined as the first conversion clock). the msb is valid 8 ns after the falling edge of the fourth conver- sion clock. the first conversion is complete after 14 clock cycles. at any time after the falling edge of the fourteenth clock cycle, sc may go low again to initiate the next conversion. when the sc goes low, the conversion starts on the rising edge of the next clock. (see the synchronized mode timing diagram in figure 5.) the data output will go to a high impedance state until the next conversion is initiated. free run mode when sc goes low, conversion starts on the next rising edge of the clock (defined as the first conversion clock). the msb data is valid 8 ns after the falling edge of the fourth conver- sion clock. as long as sc is held low, the device operates in the free run mode. new conversions start after every fourteenth cycle with valid data available 8 ns after the falling edge of the fourth clock within each new conversion cycle. the data output remains low between conversion cycles. (see the free run mode timing diagram in figure 6.)
6 12/29/99 spt7830 5 a 4 a clock data out a9 a1 t d =8 ns 1 3 a 1 4 a t d =8 ns t d =8 ns t d =8 ns msb a0 lsb v ref + analog in v ref - ground v dd data out clock sc ref in v in +v dd .01 f .01 f +v dd 0 v +v dd 0 v +v dd 0 v v ref+ 0 v figure 7 - typical interface circuit figure 8 - data output timing figure 4 - single shot mode timing diagram 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a start conversion sample analog input a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 msb lsb clock serial data out high z state 14 a t sc latch msb start convert figure 5 - synchronous mode timing diagram 1 b 2 b 3 b 4 b 5 b 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 13 a start sample analog input a start convert clock serial data out sample analog input b a9 a8 a7 a6 msb lsb a0 a1 14 a latch msb b9 latch msb t sc t sc 15 a 16 a high z state msb figure 6 - free run mode timing diagram 1 b 2 b 3 b 4 b 5 b 6 b 7 b 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 1 3 a start sample analog input a clock serial data out sample analog input b b9 b8 b7 a9 a8 a7 a6 msb lsb a0 aa aa aa aa aa aa aa aa a1 1 4 a latch msb start convert msb
7 12/29/99 spt7830 figure 9 - analog input track-and-hold timing and reference settling-and-hold timing package outline 8-lead soic a b c d e f g h i j k inches millimeters symbol min max min max a 0.187 0.194 4.80 4.98 b 0.228 0.242 5.84 6.20 c 0.050 typ 1.27 typ d 0.014 0.019 0.35 0.49 e 0.005 0.010 0.13 0.25 f 0.060 0.067 1.55 1.73 g 0.055 0.060 1.40 1.55 h 0.149 0.156 3.81 3.99 i0 8 0 8 j 0.007 0.010 0.19 0.25 k 0.016 0.035 0.41 0.89 ref hold ref settling window ** synchronous mode * single shot mode ( sc high, no b cycle) free run mode ( sc always ?) 1 a 2 a 3 a 4 a 13 a 14 a 1 b 2 b 3 b 4 b sample input sample input sc clock v ref+ a in * the rising edge of the sc line can occur any time between the rising edge of clock 1a and the falling edge of clock 14a. the reference settling window can be extended in the synchronous mode by adding extra clocks between conversion cycles. the example shown is the minimum number of clocks required (14) per conversion cycle. **
8 12/29/99 spt7830 pin assignments pin functions name function analog in analog signal input start convert start convert. a high-to-low transition on this input begins the conversion cycle and enables serial data output. clock clock that drives a/d conversion cycle and the synchronous serial data output data out serial data. tri-state serial data output for the a/d result driven by the clock input external v ref + external voltage reference for top of refer- ence ladder external v ref - external voltage reference for bottom of reference ladder v dd analog and digital +3 v to +5 v power supply input gnd analog and digital ground data out external v ref + analog in external v ref - ground v dd clock start convert 1 2 3 4 8 7 6 5 ordering information part number temperature range package SPT7830SCS 0 to +70 c 8l soic spt7830sis C40 to +85 c 8l soic spt7830scu +25 c die* *please see the die specification for guaranteed electrical performance.
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